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? 2001-2015 microchip technology inc. ds20001467c-page 1 tc7660s features ? oscillator boost from 10 khz to 45 khz ? converts +5v logic supply to 5v system ? wide input voltage range: +1.5v to +12v ? efficient voltage conversion (99.9%, typical) ? excellent power efficiency (98%, typical) ? low power consumption: 80 a (typical) @ v in = 5v ? low cost and easy to use - only two external capacitors required ? available in 8-pin small outline (soic) and 8-pin pdip packages ? improved esd protection (10 kv hbm) ? no external diode required for high-voltage operation applications ? rs-232 negative power supply ? simple conversion of +5v to 5v supplies ? voltage multiplication v out = n v + ? negative supplies for data acquisition systems and instrumentation package types general description the tc7660s device is a pin-compatible replacement for the industry standard 7660 charge pump voltage converter. it converts a +1.5v to +12v input to a corre- sponding -1.5v to -12v output using only two low-cost capacitors, eliminating inductors and their associated cost, size and electromagnetic interference (emi). added features include an extended supply range to 12v, and a frequency boost pin for higher operating fre- quency, allowing the use of smaller external capacitors. the on-board oscillator operates at a nominal fre- quency of 10 khz. frequency is increased to 45 khz when pin 1 is connected to v + . operation below 10 khz (for lower supply current applications) is possible by connecting an external capacitor from osc to ground (with pin 1 open). the tc7660s is available in 8-pin pdip and 8-pin small outline (soic) packages in commercial and extended temperature ranges. 1 2 3 4 8 7 6 5 tc7660s boost cap + gnd cap - v out low voltage (lv) osc pdip/soic v + super charge pump dc-to-dc voltage converter
tc7660s ds20001467c-page 2 ? 2001-2015 microchip technology inc. functional block diagram tc7660s gnd internal voltage regulator rc oscillator voltage level translator v + cap + 82 7 6 osc lv 3 logic network v out 5 cap- 4 ?? 2 internal voltage regulator boost 1
? 2001-2015 microchip technology inc. ds20001467c-page 3 tc7660s 1.0 electrical characteristics absolute maximum ratings? supply voltage ................................................................+13v lv, boost, and osc inputs voltage: ( note 1 ) ...................................-0.3v to (v + + 0.3v) for v + < 5.5v ......................... (v + ? 5.5v) to (v + + 0.3v) for v + > 5.5v current into lv ......................................... 20 a for v + > 3.5v output short duration (v supply ? 5.5v)............... continuous package power dissipation: (t a ? +70c) ( note 2 ) 8-pin pdip ..........................................................730 mw 8-pin soic ..........................................................470 mw lead temperature (soldering, 10s) .... ....................... +300c notice?: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. exposure to maximum rating conditions for extended periods may affect device reliability. note 1: connecting any input terminal to voltages greater than v + or less than gnd may cause destructive latch-up. it is recommended that no inputs from sources operating from external supplies be applied prior to ?power up? of the tc7660s. 2: derate linearly above +50c by 5.5 mw/c. electrical specifications electrical characteristics: unless otherwise noted, specifications measured over operating temperature range with v + = 5v, c osc = 0, refer to test circuit in figure 4-1 . parameters sym. min. typ. max. units conditions supply current (boost pin open or gnd) i + ?80160ar l = ? ??180 0c ? t a ? +70c ? ? 180 -40c ? t a ? +85c ? ? 200 -55c ? t a ? +125c supply current (boost pin = v + ) i + ??300a0c ? t a ? +70c ? ? 350 -40c ? t a ? +85c ? ? 400 -55c ? t a ? +125c supply voltage range, high v + h 3.0 ? 12 v min. ?? t a ??? max, r l = 10 k ? , lv open supply voltage range, low v + l 1.5 ? 3.5 v min. ?? t a ??? max, r l = 10 k ? , lv to gnd output source resistance r out ?60100 ? i out = 20 ma ?70120 i out = 20 ma, 0c ? t a ? +70c ?70120 i out = 20 ma, -40c ? t a ? +85c ? 105 150 i out = 20 ma, -55c ? t a ? +125c ??250 v + = 2v, i out = 3 ma, lv to gnd 0c ? t a ? +70c ??400 v + = 2v, i out = 3 ma, lv to gnd -55c ? t a ? +125c oscillator frequency f osc ? 10 ? khz pin 7 open, pin 1 open or gnd 45 boost pin = v + power efficiency p eff 96 98 ? % r l = 5 k ??? boost pin open 95 98 ? t min ? t a ? t max ; boost pin open ? 88 ? boost pin = v +
tc7660s ds20001467c-page 4 ? 2001-2015 microchip technology inc. voltage conversion efficiency v outeff 99 99.9 ? % r l = ? oscillator impedance z osc ?1?m ? v + = 2v ?100? k ? v + = 5v temperature specifications electrical characteristics: unless otherwise noted, specifications measured over operating temperature range with v + = 5v, c osc = 0, refer to test circuit in figure 4-1 . parameters sym. min. typ. max. units conditions temperature ranges operating temperature range t a 0? +70 cc suffix t a -40 ? +85 c e suffix t a -40 ? +125 c v suffix storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 8ld pdip ? ja ?89.3 ? c/w thermal resistance, 8ld soic ? ja ?148.5 ? c/w electrical specifications (continued) electrical characteristics: unless otherwise noted, specifications measured over operating temperature range with v + = 5v, c osc = 0, refer to test circuit in figure 4-1 . parameters sym. min. typ. max. units conditions
? 2001-2015 microchip technology inc. ds20001467c-page 5 tc7660s 2.0 typical performance curves note: unless otherwise indicated, c 1 = c 2 = 10 f, esr c1 = esr c2 = 1 ? , t a = 25c. see figure 4-1 . figure 2-1: unloaded oscillator frequency vs. temperature. figure 2-2: supply current vs. temperature (with boost pin = v in ). figure 2-3: output source resistance vs. supply voltage. figure 2-4: unloaded oscillator frequency vs. temperature with boost pin = v in . figure 2-5: voltage conversion. figure 2-6: output source resistance vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 12 10 0 2 4 6 8 -40 -20 0 20 40 100 60 80 oscillator frequency (khz) temperature ( c) v in = 12v v in = 5v 1000 0 200 400 600 800 -40 -20 0 20 40 100 60 80 i dd ( a) temperature ( c) v in = 12v v in = 5v i out = 20ma t a = 25 c 1.5 12 11.5 10.5 9.5 8.5 7.5 5.5 6.5 4.5 2.5 3.5 100 10 30 50 70 output source resistance ( ) supply voltage (v) in 60 50 0 10 20 30 40 -40 -20 0 20 40 100 60 80 oscillator frequency (khz) temperature ( c) v in = 12v v in = 5v without load 10k load 101.0 100.5 100.0 99.5 99.0 98.5 98.0 112 11 10 9 8 7 56 4 23 voltage conversion efficiency (%) input voltage v in (v) t a = 25 c 100 0 20 40 60 80 -40 -20 0 20 40 100 60 80 output source resistance ( ) temperature ( c) v in = 2.5v v in = 5.5v
tc7660s ds20001467c-page 6 ? 2001-2015 microchip technology inc. note: unless otherwise indicated, c 1 = c 2 = 10 f, esr c1 = esr c2 = 1 ? , t a = 25c. see figure 4-1 . figure 2-7: output voltage vs. output current. figure 2-8: supply current vs. temperature. figure 2-9: supply current vs. temperature. figure 2-10: power conversion efficiency vs. load. figure 2-11: supply current vs. temperature. 0 -2 -4 -6 -8 -10 -12 output voltage v out (v) output current (ma) 0 100 90 80 70 60 40 50 30 10 20 200 150 125 175 100 75 50 25 0 supply current i dd ( a) temperature ( c) -40 -20 0 20 40 100 60 80 v in = 12.5v v in = 5.5v 200 150 125 175 100 75 50 25 0 supply current i dd ( a) temperature ( c) -40 -20 0 20 40 100 60 80 v in = 12.5v v in = 5.5v power efficiency (%) load current (ma) boost pin = open boost pin = v + 0 10 20 30 40 50 60 70 80 90 100 60.0 55.0 50.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 9.0 7.5 6.0 4.5 3.0 2.0 1.5 1.0 200 150 125 175 100 75 50 25 0 supply current i dd ( a) temperature ( c) -40 -20 0 20 40 100 60 80 v in = 12.5v v in = 5.5v
? 2001-2015 microchip technology inc. ds20001467c-page 7 tc7660s 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . 3.1 switching frequency boost pin (boost) by connecting the boost pin (pin 1), the switching frequency of the charge pump is increased from 10 khz typical to 45 khz typical. by connecting the boost pin (pin1), to the v + pin (pin 8), the switching frequency of the charge pump is increased from 10 khz typical to 45 khz typical. 3.2 charge pump capacitor (cap + ) positive connection for the charge pump capacitor, or flying capacitor, used to transfer charge from the input source to the output. in the voltage-inverting configuration, the charge pump capacitor is charged to the input voltage during the first half of the switching cycle. during the second half of the switching cycle, the charge pump capacitor is inverted and charge is transferred to the output capacitor and load. it is recommended that a low esr (equivalent series resistance) capacitor be used. additionally, larger values will lower the output resistance. 3.3 ground (gnd) input and output zero volt reference. 3.4 charge pump capacitor (cap - ) negative connection for the charge pump capacitor, or flying capacitor, used to transfer charge from the input to the output. proper orientation is imperative when using a polarized capacitor. 3.5 output voltage (v out ) negative connection for the charge pump output capacitor. in the voltage-inverting configuration, the charge pump output capacitor supplies the output load during the first half of the switching cycle. during the second half of the switching cycle, charge is restored to the charge pump output capacitor. it is recommended that a low esr capacitor be used. additionally, larger values will lower the output ripple. 3.6 low voltage pin (lv) the low voltage pin ensures proper operation of the internal oscillator for input voltages below 3.5v. the low voltage pin should be connected to ground (gnd) for input voltages below 3.5v. otherwise, the low voltage pin should be allowed to float. 3.7 oscillator control input (osc) the oscillator control input can be utilized to slow down or speed up the operation of the tc7660s. refer to section 5.4 ?changing the tc7660s oscillator frequency? , for details on altering the oscillator frequency. 3.8 power supply (v + ) positive power supply input voltage connection. it is recommended that a low esr capacitor be used to bypass the power supply input to ground (gnd). table 3-1: pin function table pin no. symbol description 1 boost switching frequency boost pin 2cap + charge pump capacitor positive terminal 3 gnd ground terminal 4cap - charge pump capacitor negative terminal 5v out output voltage 6 lv low voltage pin. connect to gnd for v+ < 3.5v 7 osc oscillator control input. bypass with an external capacitor to slow the oscillator. 8v + power supply positive voltage input
tc7660s ds20001467c-page 8 ? 2001-2015 microchip technology inc. 4.0 detailed description 4.1 theory of operation the tc7660s contains all the necessary circuitry to implement a voltage inverter, with the exception of two external capacitors, which may be inexpensive 10 f polarized electrolytic capacitors. operation is best understood by considering figure 4-2 , which shows an idealized voltage inverter. capacitor c 1 is charged to a voltage v + for the half cycle when switches s 1 and s 3 are closed. (note that switches s 2 and s 4 are open during this half cycle.) during the second half cycle of operation, switches s 2 and s 4 are closed, with s 1 and s 3 open, thereby shifting capacitor c 1 negatively by v + volts. charge is then transferred from c 1 negatively by v + volts. charge is then transferred from c 1 to c 2 , such that the voltage on c 2 is exactly v + assuming ideal switches and no load on c 2 . the four switches in figure 4-2 are mos power switches; s 1 is a p-channel device, and s 2 , s 3 and s 4 are n-channel devices. the main difficulty with this approach is that in integrating the switches, the sub- strates of s 3 and s 4 must always remain reverse-biased with respect to their sources, but not so much as to degrade their on resistances. in addition, at circuit start-up, and under output short circuit condi- tions (v out = v + ), the output voltage must be sensed and the substrate bias adjusted accordingly. failure to accomplish this will result in high power losses and probable device latch-up. this problem is eliminated in the tc7660s by a logic network which senses the output voltage (v out ) together with the level translators, and switches the substrates of s 3 and s 4 to the correct level to maintain necessary reverse bias. figure 4-1: tc7660s test circuit. the voltage regulator portion of the tc7660s is an integral part of the anti-latch-up circuitry. its inherent voltage drop can, however, degrade operation at low voltages. figure 4-2: ideal charge pump inverter. to improve low-voltage operation, the ?lv? pin should be connected to gnd, disabling the regulator. for supply voltages greater than 3.5v, the lv terminal must be left open to ensure latch-up-proof operation and prevent device damage. 4.2 theoretical power efficiency considerations in theory, a capacitive charge pump can approach 100% efficiency if certain conditions are met: (1) the drive circuitry consumes minimal power. (2) the output switches have extremely low on resistance and virtually no offset. (3) the impedances of the pump and reservoir capacitors are negligible at the pump frequency. the tc7660s approaches these conditions for nega- tive voltage multiplication if large values of c 1 and c 2 are used. energy is lost only in the transfer of charge between capacitors if a change in voltage occurs. the energy lost is defined by: e = 1/2 c 1 (v 1 2 ? v 2 2 ) v 1 and v 2 are the voltages on c 1 during the pump and transfer cycles. if the impedances of c 1 and c 2 are rel- atively high at the pump frequency (refer to figure 4-2 ) compared to the value of r l , there will be a substantial difference in voltages v 1 and v 2 . therefore, it is desir- able not only to make c 2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for c 1 in order to achieve maximum efficiency of operation. 4.3 dos and don'ts ? do not exceed maximum supply voltages. ? do not connect the lv terminal to gnd for supply voltages greater than 3.5v. ? do not short circuit the output to v + supply for voltages above 5.5v for extended periods; how- ever, transient conditions including start-up are okay. ? when using polarized capacitors in the inverting mode, the + terminal of c 1 must be connected to pin 2 of the tc7660s and the + terminal of c 2 must be connected to gnd. 1 2 3 4 8 7 6 5 tc7660s + v + (+5v) v out c 1 10 f c osc + c 2 10 f i l r l i s v + note: for large values of c osc (>1000 pf), the values of c 1 and c 2 should be increased to 100f. v + gnd s 3 s 1 s 2 s 4 c 2 v out = -v in c 1 + +
? 2001-2015 microchip technology inc. ds20001467c-page 9 tc7660s 5.0 applications information 5.1 simple negative voltage converter figure 5-1 shows typical connections to provide a negative supply where a positive supply is available. a similar scheme may be employed for supply voltages anywhere in the operating range of +1.5v to +12v, keeping in mind that pin 6 (lv) is tied to the supply negative (gnd) only for supply voltages below 3.5v. figure 5-1: simple negative converter. the output characteristics of the circuit in figure 5-1 are those of a nearly ideal voltage source in series with a 70 ?? resistor. thus, for a load current of -10 ma and a supply voltage of +5v, the output voltage would be -4.3v. the dynamic output impedance of the tc7660s is due, primarily, to capacitive reactance of the charge transfer capacitor (c 1 ). since this capacitor is connected to the output for only half of the cycle, the equation is: equation 5.2 paralleling devices any number of tc7660s voltage converters may be paralleled to reduce output resistance ( figure 5-2 ). the reservoir capacitor, c 2 , serves all devices, while each device requires its own pump capacitor, c 1 . the resul- tant output resistance would be approximately: equation figure 5-2: paralleling devices lowers output impedance. figure 5-3: increased output voltage by cascading devices. + v + + 1 2 3 4 8 7 6 5 tc7660s v out * c 1 10 f * v out = -v + for 1.5v ? v+ ? 12v c 2 10 f x c 2 2fc 1 ----------- 3 . 1 8 ? == where: f = 10 khz and c1 = 10 f. r out r out of tc7660s ?? n number of devices ?? --------------------------------------------------- = ?n? ?1? r l + v + + 1 2 3 4 8 7 6 5 tc7660s c 1 c 2 + 1 2 3 4 8 7 6 5 tc7660s c 1 v out * ?1? + v + + 1 2 3 4 8 7 6 5 tc7660s 10 f * v out = -n v + for 1.5v ? v+ ? 12v ?n? + 1 2 3 4 8 7 6 5 tc7660s 10 f 10 f + 10 f
tc7660s ds20001467c-page 10 ? 2001-2015 microchip technology inc. 5.3 cascading devices the tc7660s may be cascaded as shown ( figure 5-3 ) to produce larger negative multiplication of the initial supply voltage. however, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. the output voltage is defined by: equation where n is an integer representing the number of devices cascaded. the resulting output resistance would be approximately the weighted sum of the individual tc7660s r out values. 5.4 changing the tc7660s oscillator frequency it may be desirable in some applications (due to noise or other considerations) to increase the oscillator fre- quency. pin 1, frequency boost pin, may be connected to v + to increase oscillator frequency to 45 khz from a nominal of 10 khz for an input supply voltage of 5.0v. the oscillator may also be synchronized to an external clock as shown in figure 5-4 . in order to prevent possi- ble device latch-up, a 1 k ? resistor must be used in series with the clock output. in a situation where the designer has generated the external clock frequency using ttl logic, the addition of a 10 k ? pull-up resistor to v + supply is required. note that the pump frequency with external clocking, as with internal clocking, will be half of the clock frequency. output transitions occur on the positive-going edge of the clock. figure 5-4: external clocking. it is also possible to increase the conversion efficiency of the tc7660s at low load levels by lowering the oscillator frequency. this reduces the switching losses, and is achieved by connecting an additional capacitor, c osc , as shown in figure 5-5 . lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (c 1 ) and the reservoir (c 2 ) capacitors. to overcome this, increase the values of c 1 and c 2 by the same factor that the frequency has been reduced. for example, the addition of a 100 pf capacitor between pin 7 (osc) and pin 8 (v + ) will lower the oscillator frequency to 1 khz from its nominal frequency of 10 khz (a multiple of 10), and necessitate a corresponding increase in the values of c 1 and c 2 (from 10 f to 100 f). figure 5-5: lowering oscillator frequency. 5.5 positive voltage multiplication the tc7660s may be employed to achieve positive voltage multiplication using the circuit shown in figure 5-6 . in this application, the pump inverter switches of the tc7660s are used to charge c 1 to a voltage level of v + ?v f (where v + is the supply voltage and v f is the forward voltage drop of diode d 1 ). on the transfer cycle, the voltage on c 1 plus the supply voltage (v + ) is applied through diode d 2 to capacitor c 2 . the voltage thus created on c 2 becomes (2v + ) ? (2v f ), or twice the supply voltage minus the combined forward voltage drops of diodes d 1 and d 2. the source impedance of the output (v out ) will depend on the output current, but for v + = 5v and an output current of 10 ma, it will be approximately 60 ? . figure 5-6: positive voltage multiplier. v out n ? v + ?? = cmos gate 1k ? v out ?1? + v + + 1 2 3 4 8 7 6 5 tc7660s 10 f 10 f v + v out + + 1 2 3 4 8 7 6 5 tc7660s c 1 c 2 v + c osc + c 2 d 1 d 2 + c 1 v out = 1 2 3 4 8 7 6 5 tc7660s v + (2 v + ) - (2 v f )
? 2001-2015 microchip technology inc. ds20001467c-page 11 tc7660s 5.6 combined negative voltage conversion and positive supply multiplication figure 5-7 combines the functions shown in figure 5-3 and figure 5-6 to provide negative voltage conversion and positive voltage multiplication simultaneously. for example, this approach would be suitable for generat- ing +9v and -5v from an existing +5v supply. in this instance, capacitors c 1 and c 3 perform the pump and reservoir functions, respectively, for the generation of the negative voltage, while capacitors c 2 and c 4 are pump and reservoir, respectively, for the multiplied pos- itive voltage. there is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin 2 of the device. figure 5-7: combined negative converter and positive multiplier. 5.7 efficient positive voltage multiplication/conversion since the switches that allow the charge pumping operation are bidirectional, the charge transfer can be performed backwards as easily as forwards. figure 5-8 shows a tc7660s transforming -5v to +5v (or +5v to +10v, etc.). the only problem is that the internal clock and switch-drive section will not operate until some positive voltage has been generated. an ini- tial inefficient pump, as shown in figure 5-7 , could be used to start this circuit up, after which it will bypass the other (d 1 and d 2 in figure 5-7 would never turn on), or else the diode and resistor shown dotted in figure 5-8 can be used to ?force? the internal regulator on. figure 5-8: positive voltage conversion. 5.8 voltage splitting the same bidirectional characteristics used in figure 5-8 can also be used to split a higher supply in half, as shown in figure 5-9 . the combined load will be evenly shared between the two sides. once again, a high value resistor to the lv pin ensures start-up. because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. by using this circuit, and then the circuit of figure 5-3 , +15v can be converted (via +7.5v and -7.5v) to a nominal -15v, though with rather high series resistance (~250 ? ). figure 5-9: splitting a supply in half. 5.9 negative voltage generation for display adcs the tc7106 is designed to work from a 9v battery. with a fixed power supply system, the tc7106 will perform conversions with input signal referenced to power supply ground. 5.10 negative supply generation for 4? digit data acquisition system the tc7135 is a 4? digit adc operating from 5v supplies. the tc7660s provides an inexpensive -5v source. (see an16 and an17 for tc7135 interface details and software routines.) + c 1 d 1 + + c 3 c 4 c 2 d 2 + v out = 1 2 3 4 8 7 6 5 tc7660s v + (2 v + ) - (2 v f ) v out = -v + v out = -v - + 1m ? v - input + 1 2 3 4 8 7 6 5 tc7660s 10 f 10 f c 1 + r l1 r l2 v out = v + ? v ? 2 50 f 100 k 50 f v + v ? 50 f + 1 m 1 2 8 7 tc7660s 3 4 6 5 + ? ?
tc7660s ds20001467c-page 12 ? 2001-2015 microchip technology inc. 6.0 packaging information 6.1 package marking information note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. 3 e 3 e tc7660se oa 1545 3 e 8-lead soic (3.90 mm) nnn example 256 8-lead pdip (300 mil) example xxxxxxxx xxxxxnnn yyww example tc7660s cpa 256 3 e tc7660s epa 256 1545 1545 3 e
? 2001-2015 microchip technology inc. ds20001467c-page 13 tc7660s b a for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging 1rwh microchip technology drawing no. c04-018d sheet 1 of 2 /hdg3odvwlf'xdo,q/lqh 3$plo%rg\>3',3@ eb e a a1 a2 l 8x b 8x b1 d e1 c c 3/$1( .010 c 12 n note 1 top view end view side view e
tc7660s ds20001467c-page 14 ? 2001-2015 microchip technology inc. microchip technology drawing no. c04-018d sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging 1rwh /hdg3odvwlf'xdo,q/lqh 3$plo%rg\>3',3@ units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a - - .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb - - .430 bsc: basic dimension. theoretically exact value shown without tolerances. 3. 1. protrusions shall not exceed .010" per side. 2. 4. notes: -- dimensions d and e1 do not include mold flash or protrusions. mold flash or pin 1 visual index feature may vary, but must be located within the hatched area. significant characteristic dimensioning and tolerancing per asme y14.5m e datum a datum a e b e 2 b e 2 alternate lead design (vendor dependent)
? 2001-2015 microchip technology inc. ds20001467c-page 15 tc7660s note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
tc7660s ds20001467c-page 16 ? 2001-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2001-2015 microchip technology inc. ds20001467c-page 17 tc7660s
tc7660s ds20001467c-page 18 ? 2001-2015 microchip technology inc. notes:
? 2001-2015 microchip technology inc. ds20001467c-page 19 tc7660s appendix a: revision history revision c (november 2015) the following is the list of modifications. 1. updated section 1.0 ?electrical characteris- tics? . 2. added temperature specifications table. 3. updated product identification system section. 4. minor typographical errors. revision b (august 2013) the following is the list of modifications. 1. added appendix a and the ?product identifi- cation system? page. 2. updated section 6.0 ?packaging information? . revision a (may 2001) ? original release of this document.
tc7660s ds20001467c-page 20 ? 2001-2015 microchip technology inc. notes:
? 2001-2015 microchip technology inc. ds20001467c-page 21 tc7660s product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device: tc7660s: dc-to-dc voltage converter temperature range: c = 0c to +70c (commercial) e = -40c to +85c (extended) v = -40c to +125c (various) package: pa = 8-lead plastic dual in-line - 300 mil body (pdip) oa = 8-lead plastic small outline - narrow, 3.90 mm body (soic) tape and reel blank = tube 713 = tape and reel (soic only) 723 = reverse tape and reel (soic only) examples: a) tc7660scpa: commercial temperature, pdip package a) tc7660scpa: commercial temperature, pdip package a) tc7660sepa: extended temperature, pdip package b) tc7660scoa: commercial temperature, soic package c) tc7660scoa713: tape and reel, commercial temperature, soic package d) tc7660seoa: extended temperature, soic package e) tc7660seoa713: tape and reel, extended temperature, soic package f) tc7660seoa723: reverse tape and reel, extended temperature, soic package [x] (1) tape and reel option note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option.
tc7660s ds20001467c-page 22 ? 2001-2015 microchip technology inc. notes:
? 2001-2015 microchip technology inc. ds20001467c-page 23 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademark of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2001-2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0013-4 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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